Pseudomorphic high electron mobility transistors (P-HEMT) have been conceived of as a structure to further enhance the electron mobility and the electron concentration of the HEMTs. Several types of P-HEMTs that have a Schottky gate structure or a pn junction gate structure have already started to be used for the high frequency communication elements, taking advantage of their high electron mobility characteristics.
Patent Document 1 and Patent Document 2 disclose an epitaxial wafer for P-HEMT. The disclosed epitaxial wafer utilizes an InGaAs layer as a strained channel layer, and an AlGaAs layer as an electron supply layer at the front and at the back. Patent Document 3 discloses an interface structure of the insulator-compound semiconductor. The interface structure includes a compound semiconductor, a spacer layer disposed on the surface of the compound semiconductor, and an insulating layer disposed on the spacer layer, and Patent Document 3 discloses that the spacer layer is a semiconductor substance having a band gap larger than the band gap of the compound semiconductor.
Patent Document 4 discloses a GaN hetero structure field effect transistor that includes a channel layer 2, an n-type barrier layer 4, a p-type base layer 6, a gate electrode 16, a source electrode 12, and a drain electrode 14. The channel layer 2 is formed by an i-GaN layer, and can be expressed by the composition formula AlxGa1-xN (0≦x≦1), for example. The n-type barrier layer 4 is for example represented by AlyGa1−yN (0≦y≦1, x<y), for example, and supplies an electron to a channel by being formed by means of an n-AlGaN layer on the channel layer 2. The p-type base layer 6 is selectively formed by means of the p-GaN layer on the barrier layer 4, and is expressed by the composition formula AlxGa1-xN (0≦x≦1), for example. Patent Document 5 discloses a heterojunction field effect transistor made of a semiconductor including a nitride formed on the wafer 1, which includes a channel layer 3 disposed on the wafer 1, a barrier layer 8 disposed on and above the channel layer 3, and a gate electrode 5 disposed on the barrier layer 8. In this heterojunction field effect transistor, a p-type semiconductor layer 7 is disposed in at least a part of the area between the gate electrode 5 and the channel layer 3 which is below the gate electrode, the p-type semiconductor layer 7 being a semiconductor including an acceptor atom.    Patent Document 1: JP2004-207471 A    Patent Document 2: JP2004-207473 A    Patent Document 3: JPH10-275806 A    Patent Document 4: Japanese Patent 4041075    Patent Document 5: JP2004-273486 A